1. Field of the Invention
The present invention relates generally to processes for semiconductor manufacturing and more particularly to source metrology, process emulation, process control, and methods for characterizing lithographic processes and scanning projection systems used in Very Large Scale Integration (VLSI) photolithography.
2. Description of the Related Art
As semiconductor manufacturers race to produce integrated circuits with greater functionality and higher speed (smaller pitch, low k1, etc.) in shorter periods of time (see, for example, SEMATECH, “Lithography Difficult Challenges”, Table 56 ITRS, 2002 update, p. 63), methods for improving process yields become more difficult and represent a gating factor for profitability. A critical, difficult, and expensive semiconductor process is lithography, where process engineers and equipment manufacturers together are expected to produce high yields in the presence of fundamental (physical) limitations related to resolution, depth of focus, and overlay control. As the semiconductor industry pushes toward the fundamental limits of optical lithography, improvements in lithographic manufacturability especially those related to lithographic simulation (including Resolution Enhanced Technology (RET) design), tool or machine characterization/correction, and methods for improving lithographic processes/yields (for example, improving depth of focus for memory devices) are necessary (see, for example, P-Yang Yan, “Method and Apparatus for Enhancing the Focus Latitude in Lithography”, U.S. Pat. No. 5,303,002, Apr. 12, 1994).
The ability to model (simulate) the lithography process, especially the projection imaging system, has proved quite successful in improving manufacturing yields related to low k1 mask fabrication and lithographic processing by giving engineers the tools to optimize processes quickly and inexpensively. Electromagnetic (E&M) simulation and lithographic process modeling is probably best discussed by Neureuther in several papers (see, for example, W. Oldham et al., “A General Simulator for VLSI Lithography and Etching Processes”, Part I Application to Projection Lithography IEEE Trans. Electron Devices, ED-26, No. 4, pp. 712-722, 1975, and M. Zuniga et al., “Reaction Diffusion in Deep-UV Positive Tone Resist Systems”, Microlithographyy Proc. of SPIE, Vol. 2438, pp. 113-124, 1995). Today, the successful development of any low k1 lithography processes (circuit design, mask, and process development) generally requires the use of wave-front engineering techniques such as phase shift mask (PSM) and optical proximity correction (OPC) which depends heavily on computation (see, for example, W. Grobman et al., “Reticle Enhancement Technology: Implications and Challenges for Physical Design”, DAC, Jun. 18-22, 2001, Las Vegas, Nev.).
In general, it should be noted that the performance of a lithographic simulator coupled with a stochastic engine is still rather limited, in the sense of being able to predict process performance, simply because the physical lithographic models require inputs (both statistical and absolute) that are typically unknown or estimated (see, for example, N. Jakatdar et al., “A Parameter Extraction Framework for DUV Lithography Simulation”, Metrology, Inspection, and Process Control for Microlithography XIII Proc. of SPIE, Vol. 3677, pp. 447-456, 1999). Lithographic simulation engines such as PROLITH™ or SOLID-C™ require approximately 100 modeling parameters (many simply unknown) for the proper simulation of the lithography process including chromatic effects. The introduction of complex chemically amplified resist (CAR) has dramatically improved lithographic imaging with the added cost of parameter heavy resist models, such as post exposure bake, non Fickian diffusion, etc., (see, for example, “Reaction Diffusion in Deep-UV Positive Tone Resist Systems”, supra). Advances in lithographic simulation, notably speed and complexity, have become vital as the industry depends on virtual process development and lithographic process optimization (see, for example, D. Gerold et al., “Multiple Pitch Transmission and Phase Analysis of Six Types of Strong Phase-Shifting Masks”, Optical Microlithography Proc. of SPIE, VOL. 3677, pp. 447-456, 1999). Hereto however, the outputs and benefits of lithographic simulation (namely, process optimization) depend strongly on the accuracy of the lithographic inputs (especially, source signature, lens aberrations, and mask description) including a good understanding of tool (machine) and process variability (see, for example, “A Parameter Extraction Framework for DUV Lithography Simulation”, supra and J. Cain et al., “Optimum Sampling for Characterization of Systematic Variation in Photolithography”, Optical Microlithography Proc. of SPIE, Vol. 4689-45). In general, the more detailed knowledge one has on the root causes of lithographic process variability and machine performance metrics (source uniformity, source signature (wavelength spectrum), aberrations, mechanics, focus) the better one can simulate lithographic behavior and optimize process performance. A powerful and flexible framework that combines collected machine subsystem performance parameters with simulation is described in “Method of Emulation of Lithographic Projection Tools”, A. Smith, U.S. Provisional Patent Application No. 60/564,094, dated Apr. 20, 2004.
Remarkable progress has been made on characterizing the lithographic projection imaging system through the combined use of simulation and novel metrology methods. For example, methods for the characterization of lens aberrations can be found in see, for example, A. Smith et al., “Apparatus, Method of Measurement and Method of Data Analysis for Correction of Optical System”, U.S. Pat. No. 5,828,455, Oct. 27, 1998 and A. Smith et al., “Apparatus, Method of Measurement and Method of Data Analysis for Correction of Optical System”, U.S. Pat. No. 5,978,085, Nov. 2, 1999. Methods for the characterization of illumination sources (including response to laser bandwidth) can be found in both see, for example, B. McArthur et al., “In-Situ Source Metrology Instrument and Method of Use”, U.S. Pat. No. 6,356,345, Mar. 12, 2002, and M. Terry et al., “Behavior of Lens Aberrations as a Function of Wavelength for KrF and ArF Lithgoraphy Scanners”, Optical Microlithgraphy Proc. of SPIE, pp. 113-124, 1995. The ability to accurately measure the performance of the projection imaging system has proved to be a valuable tool for tool acceptance, production monitoring, simulation, and advanced process control applications (see, for example, Nikon Corp., “Method of Forming and Adjusting Optical System and Exposure Apparatus, and for Determining Specification thereof and Related Computer System”, “Method of Forming and Adjusting Optical System and Exposure Apparatus, and for Determining Specification thereof and Related Computer System”, supra).
The International Technology Roadmap for Semiconductors (ITRS) roadmap predicts that the gate layer process for the sub-65 nm (MPU) lithography node requires controlling the lithographic process (lithography thru etch) to within 1-2 nm (3-sigma). The roadmap also predicts that DRAM manufacturers must control the contact layer process to within 6-8 nm (3-sigma). The depth of focus for the sub-65 nm node (assuming immersion lithography) is projected to be less than 0.2 um. As the semiconductor industry pushes toward the limits of optical lithography (k1 ˜0.25) the industry will need to find creative manufacturing solutions, especially for improving lithographic depth of focus. Several methods for improving lithographic depth-of-focus (especially for contact hole processes) using chromatic aberrations have been proposed (see, for example, I. Lalovic, “Depth of Focus Enhancement by Wavelength Modulation”, ARCH Interface, San Diego, Calif., 2003, pp. 9-15, and U.S. Pat. No. 5,303,002, supra)—these methods are referred to as chromatically enhanced lithography (CEL).
There is therefore a need to improve the determination of the chromatic response of a lithographic projection tool and producing methods for improving sub-wavelength lithographic process yield.